The present invention relates to the transportation of telecommunication data from a sending station to a receiving station via small data packets referred to as minicells using the Asynchronous Transfer Mode (ATM) protocol. More specifically, the present invention relates to a method and apparatus for detecting and correcting bit errors that may occur in the header portion of each minicell during transmission and for maintaining the alignment of the minicells.
The Asynchronous Transfer Mode (ATM) is a standard protocol for transmitting telecommunication data within a telecommunication system (e.g., a cellular telephone system). Data is transmitted in fixed-size packets called ATM cells. Each ATM cell contains a 48 octet payload and a 5 octet header. ATM is well known in the art and is commonly used for high bit rate applications (e.g., multimedia communication); however, ATM can be used to significantly improve the efficiency of low bit rate applications as well.
When ATM is used for transporting low bit rate data, such as cellular voice data, it is generally advantageous to compress the low bit rate data into small data packets, which are multiplexed into the payload of ATM cells as illustrated by process 100 in FIG. 1. By multiplexing the data packets into the ATM stream, bandwidth utilization is dramatically improved. These small data packets are referred to hereinbelow as minicells.
Minicells are similar to ATM cells because they too contain a header portion, usually 2 octets in length, and a payload portion that can vary in length. Of course, to maximize bandwidth efficiency, it is necessary to pack as many minicells as possible into each ATM cell. Since the length of each minicell payload can vary, it is sometimes necessary to divide the minicell and insert a first part into the payload of one ATM cell and a second part into the payload of the next ATM cell.
A telecommunication system that transports communication data using minicells in the manner described above must address two basic concerns. First, the receiving station must be capable of maintaining minicell alignment. Minicell alignment refers to the process of determining where each minicell starts and ends within an ATM cell so that the receiving station can properly extract the data from each ATM cell. However, the ability to maintain proper minicell alignment is highly dependent upon the accuracy of the data contained in each minicell header. The ability to maintain proper minicell alignment is especially dependent upon the accuracy of the length indicator code (LIC) in each minicell header, where the LIC defines the number of octets that make up the corresponding minicell payload. The second concern, therefore, is to effectively detect and, whenever possible, correct bit errors that occur in the minicell headers, during the transmission of the data from the sending station to the receiving station, particularly those that occur in the LICs.
In the past, detecting and correcting errors in minicell headers was accomplished by employing a minicell header integrity check (HIC) code for each and every minicell header, as is well known in the art. For example, Goran Eneroth et al., "Minicell Protocol (AALm) for Low Bit Rate Applications," (February 1996), employs a two octet minicell header 201 in each and every minicell, as illustrated in FIG. 2. The minicell header 201 includes a two bit HIC code 202. The two bit HIC code maintains the integrity of the header information with a two bit interleaved parity check. In another example, illustrated in FIG. 3, Tomohiro Ishihara, "Proposal of Short Cell Format for Low Bit Rate Voice," (December 1995), employs a two octet minicell header 301 in each and every minicell, where each header includes an HIC error detection/error correction code 302. In this example, the HIC code is a five bit cyclic redundancy code (CRC) that is capable of three bit error correction and two bit error detection. Unfortunately, these techniques are not bandwidth efficient because each minicell header must dedicate several bits to perform the header integrity check. The inefficiency becomes more pronounced as the number of minicells per ATM cell increases and the size of the minicell payloads decreases.
Pending U.S. patent application Ser. No. 08/626,000, entitled "Combined Minicell Alignment and Header Protection" discloses a minicell header error detection and correction technique that overcomes the inefficient bandwidth utilization techniques described above. It accomplishes this by replacing the HIC codes in each minicell header with a single header integrity check code, (e.g., a cyclic redundancy code), located in the last octet of the corresponding ATM cell. At the receiving station, each minicell header is extracted and then used to recompute the CRC. In order to extract each minicell header, the receiving station must rely on the LICs in each minicell header, so that the receiving station can jump one minicell header location to the next, by counting the number of payload octets in between. The receiving station hardware will continue this process until all of the minicell headers in the ATM cell have been extracted. If, however, there is but one bit error in any of the LICs, the receiving station hardware will begin subsequently jumping to incorrect locations to find the minicell headers. This sequence of compound errors drastically reduces the probability of performing error detection and error correction since CRCs work much better when there are but a limited number of bit errors to detect and correct. As the number of bit errors increases, the probability of detecting and correcting those errors decreases significantly. Moreover, the ability to maintain minicell alignment is severely impaired since that process is, as previously stated, highly dependent upon accurate minicell header information, especially accurate minicell length information.